Processor Modelling Studio

The Genesis Processor Modelling Studio™ is an integrated fraemwork, including tools, run time software libraries, flow, and methodology, for creating very fast simulation models of processor blocks and subsystems.

The Processor Modelling Studio provides a Python-based processor Instruction Set Architecture (ISA) description language to capture every aspect of the architecture to be modelled. This includes register sets, instruction set and encoding, operating modes, desired disassembly output format, and much more. As a result, any ambiguity and confusion that may be present in traditional native language design specifications is avoided.

This product provides significant productivity improvements compared to working in a pure C/C++ environment due to its established modelling methodology, flow, and tools. The Processor ISA description is used to automatically generate a large amount of model code — the user simply needs to fill in the instruction semantics using the rich runtime translation API in the Processor Modelling Studio. Instruction implementation is captured in a simple to understand, human friendly form, leaving the complexities of runtime translation and optimisation to the Processor Modelling Studio runtime library.

The Processor Modelling Studio is designed to deliver the highest simulation performance possible. The runtime translation and execution engine uses advanced just-in-time compilation techniques coupled with a state of the art host code optimisation technology. This underpins the creation of processor core models capable of running at multiple hundreds of MIPS, often much faster than the actual physical product.

Simulation models developed with the Processor Modeling Studio achieve performance for loosely timed (LT) Processor Models of the order of 500 MIPS or more on an average desktop (Dhrystone benchmark). Higher speeds are possible in excess of 1,000 MIPS for models with simpler timing. The exact performance figures achieved depend on the processor model configuration, such as timing accuracy, quantum settings, and others, which depend on the application requirements, as well as on the benchmark code executed.

While most processor core virtual IP models provide only one level of timing accuracy, for example functional (PV), processor core models created with the Processor Modelling Studio can operate in functional, untimed (UT), loosely timed (LT), and soon in approximately timed (AT) as well. The performance hit associated with the improved modelling accuracy is kept to a minimum by an efficient execution control algorithm.